| Contents |
| No$x51 Features/About |
| Memory and Register Map |
00-07 R0..R7 ;registers R0..R7 (bank 0, default)
;<--- initially SP=07 (stack incrementing at 08 and up).
08-0F R0..R7 ;registers R0..R7 (bank 1) or normal RAM
10-17 R0..R7 ;registers R0..R7 (bank 2) or normal RAM
18-1F R0..R7 ;registers R0..R7 (bank 3) or normal RAM
20-2F ;bit-addressable RAM (16x8 bits) or normal RAM
30-7F ;normal RAM
80-FF ;558 only - extra internal RAM - addressable by @Ri & SP only
|
0000-00FF AUX RAM 0100-01FF AUX RAM 0200-02FF AUX RAM ... 8000.. |
0000-7FFF ;internal EEPROM (P89CE558 only) 8000-FBFF ;external memory / user space FC00-FFFF ;internal BIOS ROM (all 558 only ?) |
80 P0 A0 P2 C0* P4 E0 A/ACC 81 SP A1 - C1 - E1 - 82 DPL A2 - C2 - E2 - 83 DPH A3 - C3 - E3 - 84 - A4 - C4 - E4 - 85 - A5 - C5 - E5 - 86* ADRSL0 A6* ADRSL2 C6* ADRSL4 E6* ADRSL6 87 PCON A7 - C7* P5 E7* ADPSS 88 TCON A8 IEN0/IEC C8* TM2IR E8* IEN1 89 TMOD A9* CML0 C9* CMH0 E9 - 8A TL0 AA* CML1 CA* CMH1 EA* TM2CON 8B TL1 AB* CML2 CB* CMH2 EB* CTCON 8C TH0 AC* CTL0 CC* CTH0 EC* TML2 8D TH1 AD* CTL1 CD* CTH1 ED* TMH2 8E - AE* CTL2 CE* CTH2 EE* STE 8F - AF* CTL3 CF* CTH3 EF* RTE 90 P1 B0 P3 D0 PSW F0 B 91 - B1 - D1 - F1 - 92 - B2 - D2 - F2 - 93 - B3 - D3 - F3 - 94 - B4 - D4 - F4 - 95 - B5 - D5 - F5 - 96* ADRSL1 B6* ADRSL3 D6* ADRSL5 F6* ADRSL7 97 - B7 - D7* ADCON F7* ADRSH 98 S0CON/SCON B8 IP0/IPC D8* S1CON F8* IP1 99 S0BUF/SBUF B9 - D9* S1STA F9* PLLCON 9A - BA - DA* S1DAT FA* XRAMP 9B - BB - DB* S1ADR FB**FMCON 9C - BC - DC - FC* PWM0 9D - BD - DD - FD* PWM1 9E - BE - DE - FE* PWMP 9F - BF - DF - FF* T3 |
* P8xCE558 only (not 8031/8051) ** P89CE558 only (not 8031/8051/P80CE558/P83CE558) IEN0,S0CON,S0BUF,IP0 are new 558-expressions for original IEC,SCON,SBUF,IPC. Accumulator may be called A or ACC. In source, ACC forces a "direct" operand. Registers at SFR addresses n*8 are bit-addressable (eg. P0,TCON,P1,etc). DPL,DPH are lower/upper bits of DPTR. |
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 F8 IP1 PT2 PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 F0 B B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 E8 IEN1 ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0 E0 A A.7 A.6 A.5 A.4 A.3 A.2 A.1 A.0 D8 S1CON CR2 ENS1 STA STO SI AA CR1 CR0 D0 PSW CY AC F0 RS1 RS0 OV F1 P C8 TM2IR T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0 C0 P4 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 B8 IP0 -- PAD PS1 PS0 PT1 PX1 PT0 PX0 B0 P3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 A8 IEN0 EA EAD ES1 ES0 ET1 EX1 ET0 EX0 A0 P2 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 98 S0CON SM0 SM1 SM2 REN TB8 RB8 TI RI 90 P1 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 88 TCON TF1 TR1 ZF0 TR0 IE1 IT1 IE0 IT0 80 P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 |
| External I/O Ports |
with internal pull-ups (Read/Write/Bit-adressable) |
| Timers |
| Timer 0 and 1 |
Bit Name Expl. 0,2 IT0,IT1 Interrupt 0,1 Type Control (0=Low, 1=Falling edge) 1,3 IE0,IE1 Interrupt 0,1 Edge Flag (0=None, 1=IRQ) 4,6 TR0,TR1 Timer 0,1 Run Control (0=Stop, 1=Run) 5,7 TF0,TF1 Timer 0,1 Overflow Flag (0=None, 1=IRQ) |
Bit Name Expl. 0-1 M0-1 Timer 0 Mode (0-3, see below) 2 C/T Timer 0 Selector (0=Timer, 1=Counter) 3 GATE Timer 0 Gating Control (0=Normal, 1=Stop Timer while /INT0=LOW) 4-5 M0-1 Timer 1 Mode (0-2, see below, 3=Timer stopped) 6 C/T Timer 1 Selector (0=Timer, 1=Counter) 7 GATE Timer 1 Gating Control (0=Normal, 1=Stop Timer while /INT1=LOW) |
0 8bit Timer/Counter TH0, each with 5bit prescaler TL0 (8048 Mode). 1 16bit Timer/Counter, TH0 and TL0 are cascaded. 2 8bit auto-reload Timer/Counter, TL0=timer/counter, TH0=reload value. 3 8bit TL0 Timer/Counter 0, plus 8bit TH0 Timer 1 (Timer 0 only). |
Timer - Incremented at fCLK/12 Counter - Incremented on Falling Edge of external input |
| Timer 2 |
Bit Name Expl.
0-1 T2MS0-1 Timer 2 Mode Select (0=Halted, 1=Timer, 2=Reserved, 3=Counter)
2-3 T2P0-1 Timer 2 Prescaler (0-3=Divide clock source by 1,2,4,8)
4 T2BO Timer 2 Byte Overflow Interrupt Flag (0=None, 1=IRQ)
5 T2ER Timer 2 External Reset Enable (0=Disable, 1=Enable)
(When enabled, T2 becomes reset on Raising Edge of RT2/P1.5)
6 T2IS0 Timer 2 Byte Overflow Interrupt Select
7 T2IS1 Timer 2 16-bit Overflow Interrupt Select
|
Bit Name Expl. 0-3 CTI0-3 CT0-3 (Capture) Interrupt Flags (0=None, 1=IRQ) 4-6 CMI0-2 CM0-2 (Compare) Interrupt Flags (0=None, 1=IRQ) 7 T2OV Timer 2 16-bit Overflow Flag (0=None, 1=IRQ) |
Bit Name Expl. 0,2,4,6 CTP0-3 Capture Register 0-3 triggered by falling edge on CT0I-CT3I 1,3,5,7 CTN0-3 Capture Register 0-3 triggered by raising edge on CT0I-CT3I |
Bit Name Expl. 0-5 SP40-45 New state for P4.0-5 upon CM0=T2 (0=Don't change, 1=Set) 6-7 TG46-47 New state for P4.6-7 upon toggle (0=Set, 1=Reset) |
Bit Name Expl. 0-5 RP40-45 New state for P4.0-5 upon CM1=T2 (0=Don't change, 1=Reset) 6-7 TP46-47 New state for P4.6-7 upon CM2=T2 (0=Don't change, 1=Toggle) |
Register Action Pins See also CM0 Set P4.0-5 STE Register CM1 Reset P4.0-5 RTE Register CM2 Toggle P4.6,7 STE and RTE Registers |
Port/Pin Alternative Function P1.0-3 CT0I-CT3I External Interrupt Inputs 2-5 (with Timer 2 Capture 0-3) P1.4 T2 T2 event input (counter mode), rising edge triggered P1.5 RT2 T2 reset input, rising edge triggered P1.6-7 - No special function P4.0-5 CMSR0-5 Compare and Set/Reset outputs on T2 match P4.6-7 CMT0-1 Compare and Toggle outputs on T2 match |
| Timer 3 (Watchdog) |
| Serial UART/RS232 Port |
Bit Name Expl. 0 RI Receive Interrupt Flag (0=None, 1=IRQ) 1 TI Transmit Interrupt Flag (0=None, 1=IRQ) 2 RB8 9th received bit (Mode0=Not used, Mode1=Stopbit, Mode2-3=Bit8) 3 TB8 9th transmit bit (Bit8, set by software, used in Mode2-3 only) 4 REN Serial Reception Enable (0=Disable, 1=Enable) 5 SM2 Receive Interrupt Mode (0=Normal, 1=See below) 6 SM1 SM1=LSB (!) of Serial Mode, see below 7 SM0 SM0=MSB (!) of Serial Mode, see below |
Mode Expl. Baudrate ;When SM2=1, set RI only if... 0/00h 8-bit Shift register fCLK/12 ;-[Reserved, SM2 should be 0] 1/40h 8-bit UART variable ;-only if received Stopbit valid 2/80h 9-bit UART fCLK/64 or /32 ;-only if received 9th bit RB8=1 3/C0h 9-bit UART variable ;-only if received 9th bit RB8=1 |
mov tmod,#00100001b ;\ init timer-1 for auto-reload at 32x2400Hz
mov th1,#0f4h ; > ("for used as gated 16-bit counter" ???)
setb tr1 ;/
|
| Serial I2C-Bus Port |
Bit Name Expl.
0-1 CR0-1 Clock Rate LSBs (MSB see below), depending on System Clock:
Clock 0 1 2 3 4 5 6 7 CR0-2 value
__Divider_60____1600__40____30____240___3200__160___120___osc.periods___
12MHz 200 7.5 300 400 50 3.75 75 100 kHz (kbit/sec)
16MHz 266.7 10 400 - 66.7 5 100 - kHz (kbit/sec)
Values higher than 100kHz for "fast-mode" I2C-bus applications only,
not compatible with older I2C-bus systems. CR0-2 used in master mode
only - slave mode automatically synchronizes to any rate up to 400kHz.
2 AA Assert Acknowledge flag (0=None, 1=Return Acknowledge)
When enabled, acknowledge is returned when:
- Own slave address or General call address is received.
- Data byte is received as master receiver or selected slave receiver.
3 SI Serial Interrupt flag (0=None, 1=IRQ)
While SI is set, SCL remains LOW and the transfer is suspended.
SI must be reset by software. IRQs are generated when:
- A START condition is generated in master mode.
- Own slave address or general call addr has been received during AA=1.
- Data byte has been received or transmitted in master mode
(even if arbitration is lost).
- Data byte has been received or transmitted as selected slave.
- STOP or START received as selected slave receiver/transmitter.
4 STO STOP Flag (0=Nope, 1=Stop/Recover)
In Master mode, issues a STOP condition to the bus. In slave mode,
recovers from error (without issuing STOP to bus). This flag is
cleared by hardware when sensing a STOP on the bus, or when ENS1=0.
5 STA START Flag (0=Nope, 1=Generate start condition, see below)
In Slave mode, start condition is generated once that the bus
becomes free. In Master mode, condition is repeatedly generated.
6 ENS1 Serial I/O Enable (0=Disable,Reset,SDA=SCL=high-Z, 1=Enable)
7 CR2 Clock Rate MSB, see CR0-1 description above
|
Bit Name Expl. 0-2 0 All Zeros 3-7 SC0-4 Status Code (with above zero-bits, 00-F8) |
08h A START condition has been transmitted 10h A repeated START condition has been transmitted 18h SLA and W have been transmitted, ACK has been received 20h SLA and W have been transmitted, /ACK received 28h DATA and S1DAT have been transmitted, ACK received 30h DATA and S1DAT have been transmitted, /ACK received 38h Arbitration lost in SLA, R/W or DATA |
38h Arbitration lost while returning /ACK 40h SLA and R have been transmitted, ACK received 48h SLA and R have been transmitted, /ACK received 50h DATA has been received, ACK returned 58h DATA has been received, /ACK returned |
60h Own SLA and W have been received, ACK returned
68h Arbitration lost in SLA, R/W as MST. Own SLA and W have been
received, /ACK returned
70h General CALL has been received, ACK returned
78h Arbitration lost in SLA, R/W as MST. General CALL has been received
80h Previously addressed with own SLA. DATA byte received, ACK returned
88h Previously addressed with own SLA. DATA byte received, /ACK returned
90h Previously addressed with general call. DATA byte has been received,
ACK has been returned
99h Previously addressed with general call. DATA byte has been received,
/ACK has been returned
A0h A STOP condition or repeated START condition has been received while
still addressed as SLV/REC or SLV/TRX
|
A8h Own SLA and R have been received, ACK returned
B0h Arbitration lost in SLA, R/W as MST. Own SLA and R have been
received, /ACK returned
B8h DATA byte has been transmitted, ACK returned
C0h DATA byte has been transmitted, /ACK returned
C8h Last DATA byte has been transmitted (AA=logic 0), ACK received
|
00h Bus error during MST mode or selected SLV mode, due to an erroneous
START or STOP condition
F8h No relevant information available, SI not set
|
MST Master R Read bit SLV Slave W Write bit TRX Transmitter ACK Acknowledgement (acknowledge bit = 0) REC Receiver /ACK Not acknowledgement (acknowledge bit = 1) SLA 7-bit slave address DATA 8-data byte to or from I2C-bus |
Bit Name Expl. 0 GC General Call address state (0=Not Recognized, 1=Recognized) 1-7 SLA0-6 Own Slave Address (00-7F) |
| Analog/Digital Converter |
Bit Name Expl. 0 ADSFE Start A/D conversion on falling edge at ADEXS-Pin (0=No, 1=Yes) 1 ADSRE Start A/D conversion on raising edge at ADEXS-Pin (0=No, 1=Yes) 2 ADCSA Scan Selected analog inputs (0=One-Time, 1=Continous) 3 ADSST Start and Status (0=Inactive/Stop, 1=Active/Start) 4 ADINT ADC Interrupt on completion of selected inputs (0=None, 1=IRQ) 5 ADPOS Reserved for future use (Always write "0") 6-7 ADPR0-1 Prescaler Control (0-3=Divide by 2,4,6,8) |
Bit Name Expl. 0-7 ADPSS0-7 Select analog input 0-7 at P5.0-7 (0=Skip, 1=Select) |
| Pulse Width Modulated Outputs |
fSTEP = fCLK / 2 / (PWMP+1) |
fPWM = fCLK / 510 / (PWMP+1) |
PWMP = fCLK / 510 / fPWM - 1 |
fCLK = 16MHz ;System clock PWMP = 30 ;fPWM = 16MHz/510/31 = 1012Hz PWM0 = 64 ;ratio = 64:191 = 40h:BFh PWM1 = 128 ;ratio = 128:127 = 80h:7Fh |
Repitition Rate: <------><------><------> each LOW:HIGH=998us (1012Hz) Output at /PWM0: __------__------__------ each LOW=248us : HIGH=740us Output at /PWM1: ____----____----____---- each LOW=496us : HIGH=492us |
| Interrupts |
TCON.1 IEN0.0 EX0 External Interrupt 0 TCON.5 IEN0.1 ET0 Timer 0 TCON.3+PLLCON.5 IEN0.2 EX1 External Interrupt 1, or Seconds Interrupt TCON.7 IEN0.3 ET1 Timer 1 S0CON.0+1 IEN0.4 ES0 SIO0 (UART) S1CON.3 IEN0.5 ES1 SIO1 (I2C) ADCON.4 IEN0.6 EAD ADC - IEN0.7 EA Global Enable (0=Disable all Interrupts) TM2IR.0-3 IEN1.0-3 ECT0-3 T2 Capture 0-3 TM2IR.4-6 IEN1.4-6 ECM0-2 T2 Compare 0-2 TM2IR.7,TM2CON.4 IEN1.7 ET2 T2 Overflow 16bit or Byte |
Address Prio Name Expl. 0003h 1 X0 External Interrupt 0 000Bh 4 T0 Timer 0 Overflow 0013h 7 X1/SEC External Interrupt 1 or Seconds Interrupt 001Bh 10 T1 Timer 1 Overflow 0023h 13 S0 SIO0 (UART/RS232) Send or Receive 002Bh 2 S1 SIO1 (I2C) 0033h 5 CT0 External Interrupt 2 with Timer 2 Capture 0 003Bh 8 CT1 External Interrupt 3 with Timer 2 Capture 1 0043h 11 CT2 External Interrupt 4 with Timer 2 Capture 2 004Bh 14 CT3 External Interrupt 5 with Timer 2 Capture 3 0053h 3 ADC ADC Completion 005Bh 6 CM0 Timer 2 Compare 0 0063h 9 CM1 Timer 2 Compare 1 006Bh 12 CM2 Timer 2 Compare 2 0073h 15 T2 Timer 2 Overflow |
Bit Name Expl. (0=Disable, 1=Enable) 0 EX0 External Interrupt 0 1 ET0 Timer 0 2 EX1 External Interrupt 1, or Seconds Interrupt 3 ET1 Timer 1 4 ES0 SIO0 (UART) 5 ES1 SIO1 (I2C) 6 EAD ADC 7 EA Global Enable (0=Disable all Interrupts) |
Bit Name Expl. (0=Disable, 1=Enable) 0-3 ECT0-3 T2 Capture 0-3 4-6 ECM0-2 T2 Compare 0-2 7 ET2 T2 Overflow |
Bit Name Expl. (0=Low, 1=High) Normal
0 PX0 External Interrupt 0 1
1 PT0 Timer 0 4
2 PX1 External Interrupt 1 7
or Seconds Interrupt 7
3 PT1 Timer 1 10
4 PS0 SIO0 (UART) 13
5 PS1 SIO1 (I2C) 2
6 PAD ADC 3
7 - Reserved for future use -
|
Bit Name Expl. (0=Low, 1=High) Normal 0-3 PCT0-3 T2 Capture 0-3 5,8,11,14 4-6 PCM0-2 T2 Compare 0-2 6,9,12 7 PT2 T2 Overflow 15 |
Bit Name Expl. 0 'IPLAL' Low Priority Interrupt Active (1=Disables all low-prio IRQs) 1 'IPLAH' High Priority Interrupt Active (1=Disables all IRQs) |
| SYS Chip Control Registers |
Bit Name Expl. 0 IDL Idle Mode (0=Normal, 1=Enter Idle Mode) 1 PD Power-Down (only if /EW=HIGH) (0=Normal, 1=Enter Power Down Mode) 2-3 GF0-1 General Purpose Flags (Allowed to be used by software) 4-6 - Unused (except on special revisions, see below) 7 SMOD Double Baudrate Timer Divider in UART mode 1-3 (0=Div 32, 1=Div 16) P8xCE558: 4 WLE Watchdog Load Enable (0=Lock, 1=Enable Write to Timer 3) 5 RFI Reduced Radio Frequency Interference (1=Suppress unused ALE pulses) 6 ARD AUX-RAM Disable (0=Enable AUX-RAM, 1=Enable External memory) 80C32/52 and up: 4 POF Power Off Flag (uh, is that a status bit, indicating coldboot?) 5-6 - Unused |
Mode CPU PWM ADC T0 T1 T2 T3 UART I2C INT0 INT1 SECINT Idle Mode - - - + + - + + + + + + Power Down - - - - - - N/A - - + + (RUN32) |
Bit Name Expl. 0-4 FSEL.0-4 System Clock Frequency Selection (default=0Dh/11.01MHz) 5 SECINT Seconds Interrupt Flag (Automatically set once per second) 6 ENSECI Seconds Interrupt Enable (1=Enable; INT1 must be enabled also) 7 RUN32 32kHz oscillator during Power Down (0=Halted, 1=Kept Running) |
0Bh=15.73MHz 0Dh=11.01MHz 0Fh=7.68MHz 11h=5.51MHz 13h=3.93MHz 0Ch=12.58MHz 0Eh=9.44MHz 10h=6.29MHz 12h=4.72MHz 0h-0Ah,14h-1Fh=Reserved |
From HIGH to LOW frequencies: First change FSEL.4-2, then FSEL.0-1 (and then better wait 1ms ?). From LOW to HIGH frequencies: First change FSEL.0-1, then wait 1ms, then change FSEL.2-4. |
Bit Name Expl. 0-1 XRAMP0-1 AUX-RAM Page Selection (0-2, 3=Reserved) 2-7 - Not used / Reserved (always write "0" to these bits) |
Bit Name Expl.
0-3 FCB0-3 Function Code
4 - Reserved, always write "0"
5 HV High Voltage Indication - Read Only
(Set while high voltage for write/erase operation is present)
6-7 UBS0-1 User/Boot Memory Selection
|
0 User memory mapped from 0 to 64K 1 User memory mapped from 0 to 63K, Boot ROM from 63K to 64K 2 Reserved/Internal 3 Reserved/Internal (User memory may be internal and/or external memory) |
00h Value after Reset 05h Byte Write or Byte Read/Verify 0Ch Page Erase (32 bytes boundaries) 03h Block Erase (256 bytes boundaries) 0Ah Full Erase (32 Kbytes) |
| CPU Microprocessor |
| CPU Registers and Flags |
Bit Name Expl. 0 P Parity of Accumulator (0=Even, 1=Odd) - Read Only 1 F1 Reserved in 8031/51 models 2 OV Overflow Flag (0=No Overflow, 1=Overflow) 3-4 RS0-1 Register Bank Select (Bank 0-3, for registers R0-R7) 5 F0 User Flag 0 (May be used for whatever purpose) 6 AC Auxiliary Carry Flag (For "DA A" opcode) 7 CY Carry Flag (0=No Carry, 1=Carry) |
Instruction CY OV AC Instruction CY OV AC Instruction CY OV AC ADD X X X CJNE X - - ANL C,bit X - - ADDC X X X RRC X - - ANL C,/bit X - - SUBB X X X RLC X - - ORL C,bit X - - MUL 0 X - SETB C 1 - - ORL C,/bit X - - DIV 0 X - CLR C 0 - - MOV C,bit X - - DA X - - CPL C X - - |
| CPU Arithmetic Operations |
Mnemonic Nocash Bytes/Cycles Description ADD A,Rn ADD A,Rn 1/1 Add register to A ADD A,direct ADD A,[nn] 2/1 Add direct byte to A ADD A,@Ri ADD A,[Ri] 1/1 Add indirect RAM to A ADD A,#data ADD A,nn 2/1 Add immediate to A ADDC A,Rn ADC A,Rn 1/1 Add register to A with Carry ADDC A,direct ADC A,[nn] 2/1 Add direct byte to A with Carry ADDC A,@Ri ADC A,[Ri] 1/1 Add indirect RAM to A with Carry ADDC A,#data ADC A,nn 2/1 Add immediate to A with Carry SUBB A,Rn SBC A,Rn 1/1 Subtract register from A with borrow SUBB A,direct SBC A,[nn] 2/1 Subtract direct byte from A with borrow SUBB A,@Ri SBC A,[Ri] 1/1 Subtract indirect RAM from A with borrow SUBB A,#data SBC A,nn 2/1 Subtract immediate from A with borrow INC A INC A 1/1 Increment A INC Rn INC Rn 1/1 Increment register INC direct INC [nn] 2/1 Increment direct byte INC @Ri INC [Ri] 1/1 Increment indirect RAM INC DPTR INC DPTR 1/1 Increment data pointer (16 bit value) DEC A DEC A 1/1 Decrement A DEC Rn DEC Rn 2/1 Decrement register DEC direct DEC [nn] 1/1 Decrement direct byte DEC @Ri DEC [Ri] 1/2 Decrement indirect RAM MUL AB MUL A,B 1/4 Multiply A & B (BA = A * B) DIV AB DIV A,B 1/4 Divide A by B (A=A/B, B=A MOD B) DA A DAA A 1/1 Decimal Adjust (after 'BCD+BCD'operation) |
| CPU Logical Operations |
Mnemonic Nocash Bytes/Cycles Description ANL A,Rn AND A,Rn 1/1 AND register to A ANL A,direct AND A,[nn] 2/1 AND direct byte to A ANL A,@Ri AND A,[Ri] 1/1 AND indirect RAM to A ANL A,#data AND A,nn 2/1 AND immediate to A ANL direct,A AND [nn],A 2/1 AND A to direct byte ANL direct,#data AND [nn],nn 3/2 AND immediate to direct byte ORL A,Rn OR A,Rn 1/1 OR register to A ORL A,direct OR A,[nn] 2/1 OR direct byte to A ORL A,@Ri OR A,[Ri] 1/1 OR indirect RAM to A ORL A,#data OR A,nn 2/1 OR immediate to A ORL direct,A OR [nn],A 2/1 OR A to direct byte ORL direct,#data OR [nn],nn 3/2 OR immediate to direct byte XRL A,Rn XOR A,Rn 1/1 Exclusive-OR register to A XRL A,direct XOR A,[nn] 2/1 Exclusive-OR direct byte to A XRL A,@Ri XOR A,[Ri] 1/1 Exclusive-OR indirect RAM to A XRL A,#data XOR A,nn 2/1 Exclusive-OR immediate to A XRL direct,A XOR [nn],A 2/1 Exclusive-OR A to direct byte XRL direct,#data XOR [nn],nn 3/2 Exclusive-OR immediate to direct byte CLR A CLR A 1/1 Clear A CPL A CPL A 1/1 Complement A RL A ROL A 1/1 Rotate A Left RLC A RCL A 1/1 Rotate A Left through the Carry RR A ROR A 1/1 Rotate A Right RRC A RCR A 1/1 Rotate A Right through the Carry SWAP A SWAP A 1/1 Swap nibbles within A (4bit rotate) CLR C CLR C 1/1 Clear carry CLR bit CLR bit 2/1 Clear direct bit SETB C SET C 1/1 Set carry SETB bit SET bit 2/1 Set direct bit CPL C CPL C 1/1 Complement carry CPL bit CPL bit 2/1 Complement direct bit ANL C,bit AND C,bit 2/2 AND direct bit to Carry ANL C,/bit AND C,/bit 2/2 AND complement of direct bit to Carry ORL C,bit OR C,bit 2/2 OR direct bit to Carry ORL C,/bit OR C,/bit 2/2 OR complement of direct bit to Carry |
| CPU Data Transfer |
Mnemonic Nocash Bytes/Cycles Description MOV A,Rn MOV A,Rn 1/1 Move register to A MOV A,direct MOV A,[nn] 2/1 Move direct byte to A MOV A,@Ri MOV A,[Ri] 1/1 Move indirect RAM to A MOV A,#data MOV A,nn 2/1 Move immediate to A MOV Rn,A MOV Rn,A 1/1 Move A to register MOV Rn,direct MOV Rn,[nn] 2/2 Move direct byte to register MOV Rn,#data MOV Rn,nn 2/1 Move immediate to register MOV direct,A MOV [nn],A 2/1 Move A to direct byte MOV direct,Rn MOV [nn],Rn 2/2 Move register to A MOV direct,direct MOV [nn],[nn] 3/2 Move direct byte to direct byte MOV direct,@Ri MOV [nn],[Ri] 2/2 Move indirect RAM to direct byte MOV direct,#data MOV [nn],nn 3/2 Move immediate to direct byte MOV @Ri,A MOV [Ri],A 1/1 Move A to indirect RAM MOV @Ri,direct MOV [Ri],[nn] 2/2 Move direct byte to indirect RAM MOV @Ri,#data MOV [Ri],nn 2/1 Move immediate to indirect RAM MOV DPTR,#data16 MOV DPTR,nnnn 3/2 Load data pointer with 16bit constant MOVC A,@A+DPTR MOVC A,[A+DPTR] 1/2 Move code byte relative to DPTR to A MOVC A,@A+PC MOVC A,[A+PC] 1/2 Move code byte relative to PC to A MOVX A,@Ri MOVX A,[Ri] 1/2 Move external RAM (8bit addr) to A MOVX A,@DPTR MOVX A,[DPTR] 1/2 Move external RAM (16bit addr) to A MOVX @Ri,A MOVX [Ri],A 1/2 Move A to external RAM (8bit addr) MOVX @DPTR,A MOVX [DPTR],A 1/2 Move A to external RAM (16bit addr) PUSH direct PUSH [nn] 2/2 Increment SP, push direct byte to SP POP direct POP [nn] 2/2 Pop direct byte from SP, decrement SP XCH A,Rn XCHG A,Rn 1/1 Exchange register with A XCH A,direct XCHG A,[nn] 2/1 Exchange direct byte with A XCH A,@Ri XCHG A,[Ri] 1/1 Exchange indirect RAM with A XCHD A,@Ri XCHD A,[Ri] 1/1 Exchange lower digit (4bit) with A MOV C,bit MOV C,bit 2/1 Move direct bit to Carry MOV bit,C MOV bit,C 2/2 Move Carry to direct bit |
| CPU Program Branching |
Mnemonic Nocash Bytes/Cycles Description ACALL addr11 ACALL addr11 2/2 Absolute subroutine call LCALL addr16 LCALL addr16 3/2 Long subroutine call RET RET 1/2 Return for subroutine RETI RETI 1/2 Return for interrupt SJMP rel SJMP rel 2/2 Short jump (8bit relative) AJMP addr11 AJMP addr11 2/2 Absolute jump (11bit absolute) LJMP addr16 LJMP addr16 3/2 Long jump (16bit long) JMP @A+DPTR JMP A+DPTR 1/2 Jump indirect relative to DPTR JZ rel JZ A,rel 2/2 Jump if A is zero JNZ rel JNZ A,rel 2/2 Jump if A is not zero CJNE A,direct,rel JNE A,[nn],rel 3/2 Cmp direct byte to A, jump if not eq CJNE A,#data,rel JNE A,nn,rel 3/2 Cmp imm to A, jump if not eq CJNE Rn,#data,rel JNE Rn,nn,rel 3/2 Cmp imm to register, jump if not eq CJNE @Ri,#data,rel JNE [Ri],nn,rel 3/2 Cmp imm to indirect, jump if not eq DJNZ Rn,rel DJNZ Rn,rel 3/2 Decrement register, jump if not zero DJNZ direct,rel DJNZ [nn],rel 3/2 Decrement direct, jump if not zero JC rel JC rel 2/2 Jump if Carry is set JNC rel JNC rel 2/2 Jump if Carry is not set JB bit,rel JNZ bit,rel 3/2 Jump if direct bit is set JNB bit,rel JZ bit,rel 3/2 Jump if direct bit is not set JBC bit,rel JNZ0 bit,rel 3/2 Jump if direct bit is set, clear bit (INT vector) (INT vector) -/2? Interrupt (LCALL to vector address) |
| CPU Notes |
Rn - Register R7-R0 of the currently selected register bank
(The register bank is selected by PSW.3 and PSW.4)
(Note that various opcodes support only <direct> operands,
but not <Rn> operands (eg. PUSH/POP). In such cases, the
assembler converts R0-R7 into direct addresses 00h-07h,
which is forcefully accessing register bank 0 only)
direct - 8-bit internal data locations's address. This could be an
internal data RAM location (0-127) or a SFR [i.e. I/O
port, control register, status register, etc. (128-255)].
@Ri - 8-bit internal data RAM location addressed indirectly
through register R1 or R0
#data - 8-bit constant included in instruction
#data16 - 16-bit constant included in instruction
addr16 - 16-bit destination address. Used by LCALL & LJMP. A
branch can be anywhere within the 64K-byte Program Memory
address space
addr11 - 11-bit destination address. Used by ACALL & AJMP. The
branch will be in the same 2K-byte page of program
memory as the first byte of the following instruction
rel - Signed (two's complement) 8-bit offset byte. Used by
SJMP and all conditional jumps. Range is -128 to +127
bytes relative to first byte of following the instruction
bit - Direct addressed bit in internal data RAM or special
function register (SFR)
|
| Flash EEPROM |
| FEEPROM User Access |
In: FMCON=45h, DPTR=Byte Address Out: FMCON=15h, A=DATA, DPTR=Unchanged |
In: FMCON=45h, A=DATA, DPTR=Byte Address Out: FMCON=15h, A=DATA (read-back), DPTR=Unchanged |
In: FMCON=4Ch, DPTR=Page Address, lower 5bits ignored Out: FMCON=1Ch, A=08h, DPTR=Unchanged, except that lower 5bits reset |
In: FMCON=43h, DPTR=Block Address, lower 8bits (DPL) ignored Out: FMCON=13h, ACC=02h, DPTR=Unchanged, except that lower 8bits reset |
In: FMCON=4Ah Out: FMCON=1Ah, ACC=0Ah, DPTR=0018h |
In: FMCON=40h, Interrupt Registers, Stack Pointer, Timer 0, UART, P3.0-1 Out: Does never return - system must be manually reset after transfer. |
| FEEPROM Security |
| FEEPROM Parallel Programming |
15 address lines, 8 data lines, 9 control lines, and one 4-6MHz oscillator at XTAL1/XTAL2 |
| FEEPROM Serial Programming |
: Record Start character BC Byte Count (number of HH data bytes in this record, 00..FF) AAAA Destination address of first byte of this record (0000..7FFF) TT Record Type (00=data record, 01=end record) HH Data Byte(s) CC Record Checksum (CC = 00-BC-AA-AA-TT-HH-HH-HH-...-HH) |
"." Acknowledges record type TT=00 received. "X" Error - Bad CC checksum. "Y" Error - Bad TT record type. "Z" Error - Buffer overflow (Check Xon/Xoff) "R" Error - Verification Error (of last byte written). "V" End record (TT=01) received, and FEEPROM programming completed. Xoff Busy. Master may not send further data. ;Xoff=chr(13h) Xon End of Busy period. Master may continue sending. ;Xon =chr(???) |
Baudrate 1200 2400 4800 9600 19200 Bauds fCLKmin 1 2 4 7.9 15.7 MHz fCLKmax 3.6 7.3 14.7 29.5 59 MHz |
| CIR Basic Connection Circuits |
| CIR Reset Circuit |
+5V ----[]|---- RSTIN
+ -
|
| CIR Oscillator (System Clock) |
XTAL3,4 Oscillator Circuit, XTAL1,2 Oscillator Circuit XTAL1 External
PLL Oscillator+Seconds Timer (Standard 80C51 compatible) Clock Input
SELXTAL1 XTAL3 XTAL4 XTAL1 XTAL2 SELXTAL1 XTAL1 SELXTAL1
| | | | | | | |
GND +-|O|-+ +-||-GND-||-+ +5V | +5V
Software-selectable system | | EXT.CLK,
clock rates of 3.93-15.73MHz +----|O|----+ 3.5-16MHz 3.5-16MHz
Use external 32768Hz crystal Use 22pF capacitors, quartz Leave XTAL2
without external capacitors. crystal or ceramic resonator. not connected.
|
| CIR Pin-Outs |
__________ __________
| \/ |
P1.0 | 01 40 | VCC
P1.1 | 02 39 | P0.0 AD0
P1.2 | 03 38 | P0.1 AD1
P1.3 | 04 37 | P0.2 AD2
P1.4 | 05 36 | P0.3 AD3
P1.5 | 06 35 | P0.4 AD4
P1.6 | 07 34 | P0.5 AD5
P1.7 | 08 33 | P0.6 AD6
RST,VPD* | 09 8051 32 | P0.7 AD7
RXD P3.0 | 10 31 | /EA
TXD P3.1 | 11 30 | ALE
/INT0 P3.2 | 12 29 | /PSEN
/INT1 P3.3 | 13 28 | P2.7 AD15
T0 P3.4 | 14 27 | P2.6 AD14
T1 P3.5 | 15 26 | P2.5 AD13
/WR P3.6 | 16 25 | P2.4 AD12
/RD P3.7 | 17 24 | P2.3 AD11
XTAL2 | 18 23 | P2.2 AD10
XTAL1 | 19 22 | P2.1 AD9
VSS | 20 21 | P2.0 AD8
|______________________|
|
1 AVref- 21 P4.2,CMSR2 41 P3.0,RXD 61 P2.6,A14 2 AVref+ 22 P4.3,CMSR3 42 P3.1,TXD 62 P2.7,A15 3 AVss1 23 RSTOUT 43 P3.2,/INT0 63 /PSEN 4 AVdd1 24 P4.4,CSMR4 44 P3.3,/INT1 64 ALE,/WE (*) 5 P5.7,ADC7 25 P4.5,CSMR5 45 P3.4,T0 65 /EA 6 P5.6,ADC6 26 P4.6,CMT0 46 P3.5,T1 66 Vdd4 7 P5.5,ADC5 27 P4.7,CMT1 47 P3.6,/WR 67 Vss4 8 P5.4,ADC4 28 Vdd2 48 P3.7,/RD 68 P0.7,AD7 9 P5.3,ADC3 29 Vss2 49 n.c. 69 P0.6,AD6 10 P5.2,ADC2 30 RSTIN 50 n.c. 70 P0.5,AD5 11 P5.1,ADC1 31 P1.0,CT0I,INT2 51 XTAL2 71 P0.4,AD4 12 P5.0,ADC0 32 P1.1,CT1I,INT3 52 XTAL1 72 P0.3,AD3 13 Vss1 33 P1.2,CT2I,INT4 53 Vdd3 73 P0.2,AD2 14 Vdd1 34 P1.3,CT3I,INT5 54 Vss3 74 P0.1,AD1 15 ADEXS 35 P1.4,T2 55 P2.0,A8 75 P0.0,AD0 16 /PWM0 36 P1.5,RT2 56 P2.1,A9 76 AVdd2 17 /PWM1 37 P1.6 57 P2.2,A10 77 AVss2 18 EW 38 P1.7 58 P2.3,A11 78 XTAL3 19 P4.0,CMSR0 39 SCL 59 P2.4,A12 79 XTAL4 20 P4.1,CMSR1 40 SDA 60 P2.5,A13 80 SELXTAL1 |
| AUX External Hardware |
| AUX Numeric Keypad |
P4.7-5 Out Select Row, 0=Select P4.4-1 Out Always output "1" to these bits P4.4-1 In Read currently selected keyboard row(s), 0=Pressed P4.0 - Not used |
0-9 --> Keypad numbers and normal numbers * --> Keypad Enter and normal Enter # --> Keypad "." and Backspace |
Ports P4.1 P4.2 P4.3 P4.4 P4.7 "1" "4" "7" "*" P4.6 "2" "5" "8" "0" P4.5 "3" "6" "9" "#" |
| AUX LCD Dot Matrix Module |
Instruction Output (RS=0): MOV DPH,#80h / MOVX @DPTR,A Data Output (RS=1, R/W=0): MOV DPH,#82h / MOVX @DPTR,A Data Input (RS=1, R/W=1): MOV DPH,#83h / MOVX A,@DPTR |
RS__R/W__D7__D6__D5__D4__D3__D2__D1__D0__Instruction___________ 0 0 0 0 0 0 0 0 0 1 Display Clear 0 0 0 0 0 0 0 0 1 * Cursor Home 0 0 0 0 0 0 0 1 I/D S Entry Mode Set 0 0 0 0 0 0 1 D C B Display on/off Control 0 0 0 0 0 1 S/C R/L * * Cursor Display Shift 0 0 0 0 1 DL 1 0 * * Function Set 0 0 0 1 <-------- Acg --------> CG RAM Address Set (0-3Fh) 0 0 1 <------------ Add --------> DD RAM Address Set (0-7Fh) 0 1 BF <------------ Ac --------> Busy Flag/Address Read 1 0 <-------- write data --------> CG/DD RAM data write 1 1 <-------- read data --------> CG/DD RAM data read |
I/D 0=Decrement, 1=Increment S 0=Display freeze, 1=Display shift D 0=Display off, 1=Display on C 0=Cursor off, 1=Cursor on B 0=Blinking off, 1=Character at Cursor position blinking S/C 0=Cursor move, 1=Display shift R/L 0=left shift, 1=right shift DL 0=4bits, 1=8bits BF 0=Not busy, 1=Internal operation busy * Don't care (?) |
Line 1 00h 01h 02h 03h 04h 05h 06h 07h 40h ... 47h (!) |
Line 1 00h 01h 02h 03h 04h 05h 06h 07h 08h ... 0Fh Line 2 40h 41h 42h 43h 44h 45h 46h 47h 48h ... 4Fh |
Line 1 00h 01h 02h 03h 04h 05h 06h 07h 08h ... 26h 27h Line 2 40h 41h 42h 43h 44h 45h 46h 47h 48h ... 66h 67h |
00h-07h CG RAM (1-8) 08h-0Fh CG RAM (1-8) 10h-1Fh Undefined 20h-7Fh Normal ASCII charcters (*) 80h-9Fh Undefined A0h-FFh Japanese/European characters |
| AMT630A - Memory Map |
0000h..7FFFh Fixed (always 1st 32Kbytes of SPI FLASH memory) 8000h..FFFFh Mappable (usually 2nd 32Kbytes of SPI FLASH memory) |
00h..07h Standard CPU registers R0-R7 (bank 0) 08h..7Fh Standard RAM 80h..FFh Extended RAM, 80C52-style (via indirect [R0],[R1],[SP]) 80h..FFh Standard+Extended SFR Registers (via direct [imm]) |
0000h..07FFh Extra RAM (2Kbytes) 0800h..1FFFh Mirror of SPI FLASH addresses 000800h..001FFFh (read only) 2000h..2FFFh Unknown (hardware status regs ?) (read only) 3000h..FAFFh Unused (open-bus) FB00h..FBFFh I/O Ports (OSD on-screen display) FC00h..FCFFh I/O Ports (LCD screen ratio) FD00h..FDFFh I/O Ports (Misc, ADC, PWM, PLL, PIN, FLASH, etc.) FE00h..FEFFh I/O Ports (AV video input) FF00h..FFFFh I/O Ports (LCD colors/brightness and IR Infrared) |
BGMAP RAM: 200h entries (each 10bit character number plus 7bit attribute) FONT RAM: 1000h words (aka 2000h bytes, aka 8Kbytes) FONT ROM: 418 characters (16x22pix, 1bpp; uppercase text & exotic symbols) |
0000h reset firmware reset vector (and apparently watchdog, too) 0003h infrared firmware has IR infrared handler (in some versions) (ext.0) 000Bh timer 0 firmware has dummy timer 0 reload handler 0013h spi flash firmware has no handler for this (ext.1) 001Bh timer 1 firmware has timer 1 handler (sensing AV signal etc) 0023h uart firmware has no handler for this 002Bh timer 2 firmware has no handler for this (80C52-style extension) 0033h ? firmware has no handler for this 003Bh ? (if any) firmware has no handler for this (are there IEC/IPC bits?) 0043h ADC firmware acknowledges SFR_IO_xxx91h.bit4 and IO_ADC_status 004Bh ? firmware acknowledges SFR_IO_xxx91h.bit5 0053h ? firmware acknowledges SFR_IO_xxx91h.bit6 005Bh framerate firmware acknowledges SFR_IO_xxx91h.bit7 (vblank/vsync?) 0063h timer 3+4 firmware has no handler for this (timer 3+4 and SFR D8h) |
3000h..FAFFh - Unused (open-bus) (CB00h bytes) FB8Ah..FBFFh - Unused (open-bus) (76h bytes) FC11h - Unused (open-bus) (01h byte) FC47h..FC8Fh - Unused (open-bus) (49h bytes) FCB9h..FCBAh - Unused (open-bus) (02h bytes) FCEBh..FCFFh - Unused (open-bus) (15h bytes) FD60h..FDAFh - Unused (open-bus) (50h bytes) FDE8h..FDEFh - Unused (open-bus) (08h bytes) FDF2h..FDFFh - Unused (open-bus) (0Eh bytes) FEFFh - Unused (open-bus) (01h byte) FFA4h..FFAFh - Unused (open-bus) (0Ch bytes) FFDDh - Unused (open-bus) (01h byte) FFEBh..FFEFh - Unused (open-bus) (05h bytes) FFFCh..FFFFh - Unused (open-bus) (04h bytes) |
| AMT630A - SFRs - System Timers/Ports/etc |
PCON.4 unknown (read-only, always 1) ;maybe whatever 80C52-style POF bit? PCON.5 unknown (read-only, always 1) PCON.6 unknown (read/write-able) IEC.5 and IPC.5 probably 80C52-style Timer2 interrupt (read/write-able) IEC.6 and IPC.6 unknown... some extra interrupt? (read/write-able) |
____________________ AMT630A-specific Non-standard SFR's ____________________ |
0 Enable IRQ 0043h (adc) 1 Enable IRQ 004Bh 2 Enable IRQ 0053h 3 Enable IRQ 005Bh (vblank/vsync or so) 4 Enable IRQ 0063h (timer3+timer4) 5-7 Unknown, not R/W (usually/always 111b) |
0-4 Seems to be related to SFR E8h.bit0-4, see there 5-7 Unknown, not R/W (usually/always 111b) |
0-3 Unknown, NOT R/W 4 Write 0 for IRQ 0043h acknowledge (ADC) ;also need to ack IO_ADC_status 5 Write 0 for IRQ 004Bh acknowledge 6 Write 0 for IRQ 0053h acknowledge 7 Write 0 for IRQ 005Bh acknowledge (vblank/vsync or so) |
There seem to be 7 interrupt sources in IEC/IPC There seem to be 5 interrupt sources in E8h/F8h And Reset/Watchdog might be the 13th interrupt source. However, there seem to be 14 exception vectors in total (including reset). |
0 DANGER: causes reboot when changed 1 Unknown, NOT R/W 2 Unknown 3 Disable OSD TEXT rendering (should be set during FLASH-to-FONT DMA) 4-6 Unknown 7 Firmware sets bit7 upon power-up, DANGER: hangs when changed |
0-2 Unknown, not R/W ;not R/W 3 Unknown, somehow forces IRQ 0063h (timer3+4)? ;R/W 4 Unknown ;R/W 5 Unknown, once seemed to make CPU 21.25x slower? ;R/W 6 Unknown, not R/W ;not R/W 7 Unknown ;R/W |
0-15 Incrementing Timer value (R/W) |
Timer 3 is faster Timer 4 is slower (4x slower than Timer 3) |
0 Timer 3 overflow flag, not R/W (1=overflow occurred) 1 Timer 4 overflow flag, not R/W (1=overflow occurred) 2-7 Unknown/unused, not R/W |
0 Unknown/unused 1 Acknowledge Timer 3 overflow (0=No change, 1=Clear overflow flag) 2 Acknowledge Timer 4 overflow (0=No change, 1=Clear overflow flag) 3-7 Unknown/unused |
0 Timer 3 IRQ Enable (when master enable in SFR E8h.bit4 is set) 1 Timer 4 IRQ Enable (when master enable in SFR E8h.bit4 is set) 2-7 Unknown/unused, not R/W |
A B 4bit 0 1 x000 Digital.output (eg. for LCD SPI writes, or static backlight) 1 0 x000 Digital.input (eg. for LCD SPI reads) 1 1 xxxx ADC (analog/digital converter, eg. keypad button read) x x xx11 PWM (pulse-width output, eg. for dimmed backlight) x x 0001 LCD 3.5" (RGB+CLK+DEN+SYNC) and SPI FLASH pins x x 0002 LCD 4.3" (RGB+CLK+DEN) 1 0 xxxx REMOTE (infrared IR input) |
0-7 Command from REMOTE (further stuff is in FFxxh register area) |
0 Flag (maybe new command?) 1 Flag (maybe repeat?) 2 Unknown (usually 0, but I think've seen the register being 04h once) 3-7 Unknown (usually 0) |
| AMT630A - FBxxh - OSD Registers (On-Screen Display) |
_______________________________ Window 0..4 _______________________________ |
0-6 Horizontal Window Size in Characters (1..127) 7 Not used (always 0) |
0-5 Vertical Window Size in Characters (1..63) 6-7 Not used (always 0) |
0-2 Upper 3bit of 11bit Horizontal Window position 3 ??? 4-6 Upper 3bit of 11bit Vertical Window position 7 Upper 1bit of 9bit Window's BGMAP Address ;Window 0: Not used (always 0) |
0-7 Lower 8bit of 11bit Horizontal Window position (0..7FFh) (10=leftmost) |
0-7 Lower 8bit of 11bit Vertical Window position (0..7FFh) (12=topmost) |
0-7 Lower 8bit of 9bit Window's BGMAP Address (0..1FFh) |
______________________________ Control Regs _______________________________ |
0-4 Enable Window 0..4 (0=Off, 1=On) 5 ??? 6 Disable 1bpp Text (0=Normal, 1=Force all 1bpp Tiles Black) 7 Enable 4bpp Bitmap (0=Off, 1=4bpp for IO_OSD_bitmap_start and up) |
0-5 ??? 6 SemiTransparency Enable for BG (0=Solid, 1=SemiTransp) 7 SemiTransparency Enable for TEXT (0=Solid, 1=SemiTransp, if bit6=1) |
0-2 SemiTransparency (0=OsdIsInvisible, 1..7=more and more opaque) 3-4 ??? 5-7 Brightness (0=Black, 1=Dark, 2=Med, 3=Bright, 4=Max/Normal, 5..7=Crop) |
0-3 ??? 4 Xflip Tiles (0=Normal; 1st Pixel (MSB) is left, 1=Mirror Horizontally) 5 Xflip BGMAP (0=Normal; 1st Tile is left, 1=Mirror Horizontally) 6 Yflip Tiles (0=Normal; 1st Pixel-row is upper, 1=Mirror Vertically) 7 Yflip BGMAP (0=Normal; 1st Tile-row is upper, 1=Mirror Vertically) |
xloc = osd_base_x + xloc ;\normal yloc = osd_base_y + yloc ;/ xloc = osd_base_x + screen_width - window_width - xloc ;\flipped yloc = osd_base_y + screen_height - window_height - yloc ;/ |
0-2 ??? 3 Affects Horizontal Window positions (0=Normal, 1=Shift SOME pixels) 4 Bitmap Color 0 (aka 4bpp tiles) (0=Transparent, 1=Solid) 5 Affects Vertical Window positions (0=Normal, 1=Shift ONE pixel) 6-7 Not used (always 0) |
0 ??? (cleared by firmware; alongsides when disabling the 5 windows) 1-7 ??? |
0 Move windows 2pix DOWN, and SOME pix LEFT 1 Jitters! Scanline 1pix shift (with AV: each 2nd line, no AV: each 3rd) 2 ??? 3 Move windows SOME pix DOWN (bottom-most pixels wrap to top of screen) 4-7 Not used (always 0) |
_______________________________ Window Scale _______________________________ |
0-31 Scale 1st..32th pixel within Font tile (bit0=topmost) (0=No, 1=Scale) |
0-23 Scale 1st..24th pixel within Font tile (bit0=leftmost) (0=No, 1=Scale) |
0-1 Window 0 Horizontal Scale (0=Double, 1=Triple, 2=Quad, 3=FiveX) 2-3 Window 0 Vertical Scale (0=Double, 1=Triple, 2=Quad, 3=FiveX) 4-7 Not used (always 0) |
0-1 Window 1 Horizontal Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 2-3 Window 1 Vertical Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 4-5 Window 2 Horizontal Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 6-7 Window 2 Vertical Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) |
0-1 Window 3 Horizontal Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 2-3 Window 3 Vertical Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 4-5 Window 4 Horizontal Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) 6-7 Window 4 Vertical Scale (0=Normal, 1=Double, 2=Triple, 3=Quad) |
______________________________ Window Palette ______________________________ |
0-3 Red (0-10) ;(11-15 are SAME as 10) ;\LSB (second byte) (!) 4-7 Green (0-10) ;(11-15 are SAME as 10) ;/ 8-11 Blue (0-10) ;(11-15 are SAME as 10) ;\MSB (first byte) (!) 12-15 Not used (always 0) ;/ |
_______________________________ BGMAP Memory _______________________________ |
0-7 Lower 8bit of 9bit BGMAP Address (0..1FFh) ;-LSB 8 Upper 1bit of 9bit BGMAP Address ;\MSB 9-15 Not used (always 0) ;/ |
0-7 Lower 8bit of 10bit Character Number (0..3FFh) ;-LSB 8-9 Upper 2bit of 10bit Character Number (0..3FFh) ;\MSB 10-15 Not used (always 0) ;/ |
0-2 Text Color (0=Transparent, 1..6=Variable, 7=Black) 3 ??? 4-6 Background Color (0=Transparent, 1..6=Variable, 7=Black) 7 Not used (always 0) |
200h entries (each entry is 10bit character number plus 7bit attribute) |
000h..1BFh Fixed ROM Font (1bpp, with color attributes) 1C0h..xxxh Custom RAM Font (1bpp, with color attributes) xxxh..xxxh Custom RAM Font (4bpp, aka "16-color bitmap") xxxh..3FFh Not useable (unless char height<8) (due to font ram limit) |
_______________________________ FONT Memory ________________________________ |
0-7 Lower 8bit of 12bit Font Address (0..FFFh) ;-LSB 8-11 Upper 4bit of 12bit Font Address ;\MSB 12-15 Not used (always 0) ;/ |
0-7 Lower 8bit of 16bit Word (bit0=leftmost pixel) ;-LSB 8-15 Upper 8bit of 16bit Word ;-MSB |
0-4 Horizontal Character Size in pixels (1..24) (25..32=glitchy) (0=32) 5-7 Not used (always 0) |
0-5 Vertical Character Size in pixels (1..32) (33..63=glitchy) (0=freeze) 6-7 Not used (always 0) |
0-7 Lower 8bit of 10bit Character Number (0..(3FFh-1C0h)) ;-LSB 8-9 Upper 2bit of 10bit Character Number (0..(3FFh-1C0h)) ;\MSB 10-15 Not used (always 0) ;/ |
1bpp characters = 1C0h..1FFh (40h characters) 4bpp characters = 200h and up |
1bpp characters = 1C0h..1FFh (40h characters) 4bpp garbage = 200h..21Fh (20h characters) 4bpp characters = 220h and up |
000h Space 001h..00Ah Digits "0..9" 00Bh..024h Letters "A..Z" (uppercase only) 025h..02Bh Letters "ZSCNLZE" (with accent marks) 02Ch..04Ch Cyrillic Letters (in uncommon order) 02Dh..030h Symbols "<", ">", Arrow/TriangleLeft, Arrow/TriangleRight 031h..032h Symbols for Enter (left, right half) 033h..037h Symbols for Striped Bar (with 0,1,2,3,4 bars) 038h..039h Symbols for Double Arrows (Up+Down, and Right+Left) 03Ah..040h Symbols for Solid Bar (LeftEdge, 0,1,2,3,4 bars, RightEdge) 041h..042h Symbols for Sound or so (SpeakerX and "o))") 043h..0D3h Japanese and/or chinese or so 0D4h..0D5h Symbols for Alert (left, right half) 0D6h..105h Japanese and/or chinese and/or whatever or so 106h..10Bh Symbols for Contrast, Brightness, Palette (left, right halves) 10Ch "." 10Dh "'C" 10Eh..131h Japanese and/or chinese and/or whatever or so 132h..133h Symbol for HandWithFingerRight and ZigZagParagraph 134h ":" 135h "!" 136h "?" 137h..13Bh Symbols for Battery (0,1,2,3 bars, and right half) 13Ch..15Ch Letters "AAAAAAEEEEUUUUIIIIIOOOOOODNGZYYap" (with accent marks) 15Dh..15Fh Symbols for upper border ".---." 160h..164h Letters "zShoC" (with accent marks/variants) 165h..17Ah Japanese and/or chinese and/or dental or so 17Ch..17Dh Symbols for left/right border "|" and "|" 17Eh..197h Japanese and/or chinese and/or dental or so 198h..19Ah Symbols for lower border "'---'" 19Bh..19Eh Japanese and/or chinese and/or dental or so 19Fh Symbol for ClockfaceTrifoldYingYang or so 1A0h Overscore 1A1h Underscore "_" with clean line 1A2h Underscore "_" with noisy line 1A3h..1BFh Unused (solid 16x22pix rectangle's) |
1000h words (aka 2000h bytes, aka 8 Kbytes) |
1-8 9-16 17-24 25-31 32 ;<-- pixels msb(0) lsb(0) msb(ysiz+0) blank buggy ;1st row msb(1) lsb(1) lsb(ysiz+0) blank buggy ;2nd row msb(2) lsb(3) msb(ysiz+1) blank buggy ;3rd row msb(3) lsb(3) lsb(ysiz+1) blank buggy ;etc. |
1-4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 msb0 lsb0 msb1 lsb1 msb2 lsb2 msb3 lsb3 msb4 lsb4 msb5 lsb5 msb6 lsb6 buggy |
_________________________BGMAP+FONT Memory Notes __________________________ |
20x25 tiles bgmap, 16x8 pixel tiles at 1bpp = 320x200 pixels |
____________________________ Unknown Registers ____________________________ |
FB2Ah - bit7:NOT R/W |
FB63h - fully R/W FB64h - fully R/W FB65h - fully R/W FB66h - fully R/W FB67h - bit7:NOT R/W FB68h - fully R/W FB69h - fully R/W FB6Ah - bit7:NOT R/W FB6Bh - fully R/W FB6Ch - fully R/W FB6Dh - fully R/W FB6Eh - fully R/W FB6Fh - fully R/W |
FB71h - bit1-7:NOT R/W FB72h - fully R/W FB73h - fully R/W FB74h - fully R/W FB75h - fully R/W |
FB79h - bit6-7:NOT R/W FB7Ah - bit6-7:NOT R/W FB7Bh - bit7:NOT R/W FB7Ch - bit7:NOT R/W FB7Dh - bit4-7:NOT R/W FB7Eh - bit6-7:NOT R/W FB7Fh - bit6-7:NOT R/W FB80h - bit6-7:NOT R/W FB81h - bit7:NOT R/W FB82h - bit7:NOT R/W FB83h - bit4-7:NOT R/W FB84h - bit6-7:NOT R/W FB85h - bit6-7:NOT R/W FB86h - bit6-7:NOT R/W FB87h - bit7:NOT R/W FB88h - bit7:NOT R/W |
| AMT630A - FCxxh - LCD Registers (mostly 50Hz/60Hz/Ratio) |
______________________ 60Hz/NTSC and 50Hz/PAL Registers ______________________ |
FC91h..FCB6h - IO_60HZ_xxx : used for 60Hz/NTSC (also used for 60Hz/PAL60) FCBDh..FCE2h - IO_50HZ_xxx : used for 50Hz/PAL (and probably 50Hz/SECAM) |
1 Move Whole Image ca.80pix LEFT 3 AV Black/Off 5 Weird Diagonal/striped AV Image (ignoreHsync?), 6 PAL: MoveWholeImageCa.12pixDOWN 6 PAL60: ContrastOnPAL60colorError 6 C64: shows SNOW with downwards rolling VSYNC from C64) 8 AV Edgy/Diagonal Color Error, 8 C64: shows SNOW with upwards rolling VSYNC from C64) 11 PAL: AV diagonally messed (ignoredHsync?) 11 PAL60: AV_MOSTLY_BLACK_except_right_edge_and_lowerleft_corner 18 PAL: MoveWholeImageCa.160pixLEFT, 18 PAL60: MoveWholeImageCa.80pixRIGHT, 19 PAL: MoveWholeImageCa.32pixDOWNandWeakPixels 19 PAL60: ContrastOnPAL60colorError |
60Hz/NTSC: 03C8h,01E3h (aka decimal 968,483) 50Hz/PAL: 0466h,0236h (aka decimal 1126,566) |
60Hz/NTSC: both=0000h, osd=0044h, av=0043h, ratio=10h (or unused:1Dh) 50Hz/PAL: both=0002h, osd=0036h, av=0043h, ratio=06h (or unused:0Ch) |
60Hz/NTSC: x=018Ah, y=0010h, ratio/upper=00h, ratio/lower=00h 50Hz/PAL: x=0192h, y=000Ch, ratio/upper=00h, ratio/lower=00h |
60Hz/NTSC: both=0007h, osd=0009h 50Hz/PAL: both=0008h, osd=0009h |
60Hz/NTSC: 0110h 50Hz/PAL: 010Fh |
NTSC at "16:9" A=0861h, B=0000h NTSC at "4:3" A=087Eh, B=0000h NTSC at (unused) A=035Bh, B=0009h PAL at "16:9" A=085Ch, B=0000h PAL at "4:3" A=0884h, B=0000h PAL at (unused) A=0363h, B=0006h |
_________________________ General Control Registers _________________________ |
bit0 On PAL50: causes VerticalScale (force NTSC resolution?), bit5 Swap AV colors Red & Blue bit7 MinorEffectOnRightScreenEdge |
0-3 Color swap for AV and OSD (ie. LCD databus mode) 4-7 Unknown, no visible effect on PAL+PAL60 image |
__________________________ More Internal Registers __________________________ |
0 Unknown, read-only (1) 1 Unknown, read-only (zero) 2 Unknown, read/write-able (usually zero, no visible effect when changed) 3-7 Unknown, read-only (zero) |
with PSX/PAL: toggles 11Dh/11Eh with Commodore C64 toggles 11Bh/11Ch with ZX Spectrum toggles 11Ch/11Dh with SNES/PAL: toggles 11Ch/11Dh with SNES/PAL60: toggles 117h/118h (and has BlackWhiteDither/wrong color) without signal increasing 0..1xxh |
FC09h.bit5-7:NOT RW ;- FC0Dh.bit6-7:NOT RW ;- FC0Fh.bit6-7:NOT RW ;- FC13h.bit4-7:NOT RW ;- FC19h.bit3-7:NOT RW ;\ FC1Bh.bit3-7:NOT RW ; FC1Dh.bit3-7:NOT RW ; FC1Fh.bit3-7:NOT RW ; FC21h.bit3-7:NOT RW ; FC23h.bit3-7:NOT RW ; FC25h.bit3-7:NOT RW ; FC27h.bit3-7:NOT RW ; FC29h.bit3-7:NOT RW ; FC2Bh.bit3-7:NOT RW ; FC2Dh.bit3-7:NOT RW ; FC2Fh.bit3-7:NOT RW ;/ FC31h.bit2-7:NOT RW ;\ FC33h.bit2-7:NOT RW ;/ FC44h.bit4-7:NOT RW ;- FC46h.bit6-7:NOT RW ;- |
| AMT630A - FDxxh - Misc Registers (PWM,ADC,PLL,PIN,SPI-FLASH) |
_______________________________ PWM Registers _______________________________ |
PWM Duty Whole System -- Backlight Part duty 100% (aka HIGH) = 290mA (1.45W) -- 234mA (1.17W) duty 50% = 65mA (0.33W) -- 9mA (0.05W) duty 0% (aka LOW) = 56mA (0.28W) -- 0mA (0W) |
0 PWM0 Enable (0=Disable, 1=Enable) ;LCD Backlight 1 PWM1 Enable (0=Disable, 1=Enable) ;LCD Config, SPI.DTA 2 PWM2 Enable (0=Disable, 1=Enable) ;LCD Config, SPI.CLK and SPI./RESET 3 PWM3 Enable (0=Disable, 1=Enable) ;LCD Config, SPI./CS 4-7 PWM0..3 Invert Flags (0=Normal/Duty=HIGH, 1=Invert/Duty=LOW) |
0-15 Total Duty, in 26MHz cycles (for HIGH and LOW periods) |
0-15 Duty HIGH, in 26MHz cycles (for HIGH period) (or LOW when inverted) |
_______________________________ ADC Registers _______________________________ |
04F0h..05BFh (avg=0564h) ;1.0K ohm (button +) (used as Up/Right) 07A0h..086Fh (avg=0804h) ;2.0K ohm (button menu) (Menu) 0AD0h..0B9Fh (avg=0B38h) ;4.7K ohm (button -) (used as Down/Left) |
0300h..03D7h (avg=03A5h) ;Menu+Plus+Minus 03D8h..046Fh (avg=040Bh) ;Menu+Plus 0450h..04EFh (avg=04B4h) ;Plus+Minus 0650h..06FFh (avg=06A1h) ;Menu+Minus 0FA0h..0FFFh (avg=0FF5h) ;(when no button pressed) xxxxh ;(invalid, might happen on transitions) |
0 Unknown (initially set to 0, this bit isn't R/W though) (R) or (W)? 1-2 Unknown (initially set to 0, hangs ADC when setting bit1 or bit2) 3 Channel 0 Run ;\firmware sets ONE of these bits on conversion start 4 Channel 1 Run ; (and clears the other three bits) 5 Channel 2 Run ; (required to be "1", ie. start/enable?) 6 Unknown VCOM? ;/ 7 Unknown (initially set to 0) 8-11 Unknown (initially set to 1111b) (not required, can be 0) 12 Unknown VCOM? ;\firmware sets ONE of these bits on conversion start 13 Channel 0 ; (and clears the other three bits) 14 Channel 1 ; (not required to be "1", can be "0") 15 Channel 2 ;/ |
0-1 Unknown, maybe channel 0 related 2 Channel 0 Ready (0=Busy, 1=Ready) 3-4 Unknown, maybe channel 1 related 5 Channel 1 Ready (0=Busy, 1=Ready) 6-7 Unknown, maybe channel 2 related 8 Channel 2 Ready (0=Busy, 1=Ready) 9-10 Unknown, maybe channel VCOM? related 11 Channel VCOM? Ready (0=Busy, 1=Ready) 12-15 Unknown |
0-11 Conversion result (0..FFFh) 12-15 Always 0 (assuming ADC cannot be configured to more than 12bit) |
0-6 Unknown, read-only (contains value 1Fh) (R) 7 Unknown, read/write-able (R/W) |
0-3 Unknown (R/W) 4-7 Unused (not R/W) |
____________________________ SPI FLASH Registers ____________________________ |
01h = Manual read JEDEC Chip ID 02h = Manual read Write-Protect-Status 04h = Manual write Write-Protect-Status 08h = Manual send FLASH command (used for WREN and ERASE) 10h = Manual read FLASH-to-CPU 20h = unknown (not used by firmware) 40h = DMA read FLASH-to-FONT 80h = DMA write XRAM-to-FLASH (max 100h bytes at once) |
0 BUSY Busy (should be 0) 1 WEL Write Enable Latch (should be 0) 2-4 BP0-2 Number of 64Kbyte Blocks to protect (0=none, 1..7=see below) 5 TB Protect Top/Bottom Blocks (0=Top, 1=Bottom) 6 - Reserved (should be 0) 7 SRP Status Register Protect when /WP=LOW (0=No, 1=Protect if /WP=LOW) |
BP=00h Protect nothing (unlock all blocks) BP=01h Protect 1 block (64Kbytes) BP=02h Protect 2 blocks (128Kbytes) BP=03h Protect 4 blocks (256Kbytes) BP=04h..07h Same as 00h..03h ;-on W25D10/W25D20 BP=04h Protect 8 blocks (512Kbytes) ;\on W25D40/W25D80 BP=05h..07h Protect all blocks (1024Kbytes) ;/ |
0-6 Maker bit1-7 (EFh/2 for Winbond) 7-14 Device Capacity (13h for Winbond W25D40) 15-22 Device Type (40h for Winbond W25D40) 23 Maker bit0 (?) (EFh and 01h for Winbond) |
0-23 Address in SPI FLASH memory (for read/write/erase operations) |
0-14 Address in XRAM or FONT memory (for DMA, not used for manual CPU read) 15 Unknown, used! (maybe DIRECTION, or maybe XRAM vs FONT select?) |
0-15 Transfer length in bytes (MINUS 1) (for DMA, not used for manual read) |
0-7 Ready flags (corresponding to start.bits in FDD0h) (1=Ready) |
0-6 Unknown/unused 7 FLASH Status (0=busy, 1=ready) |
04h Write Disable (WEL/WREN=0) (used for whatever reason) 06h Write Enable (WEL/WREN=1) (used before Erase, Write,and WriteWprot) 20h Erase 1000h-byte Sector (used when saving settings) D8h Erase 10000h-byte Block (used in an unused table entry in old firmware) D7h Erase whatever? (used in an unused table entry in old firmware) |
0 hangs and draws TWO garbage characters on OSD? 1 hangs and draws TWO garbage characters on OSD? 2 hangs and draws TWO garbage characters on OSD? 3 jumps to a pushed retadr at some/several stages higher stack level? 4 hangs and draws ONE garbage character on OSD? 5 hangs 6 hangs 7 hangs |
0-3 SPI Base Address for CODE at 8000h-FFFFh in 32Kbyte units (usually 01h) 4-7 Probably MSBs of above (no effect on 512Kbyte flash chip) |
_______________________________ PIN Registers _______________________________ |
bit5:KillTftUpdating (force dotclk stuck/low) |
FD59h.bit2 add some zigzag noise on dotclk ;\normally square wave gets FD59h.bit3 add more zigzag noise on dotclk ;/zigzag at raising/falling edges |
FC00h - IO_LCD_color_swap (color swap, eg. RGB vs BGR or so) FD34h..FD43h - IO_PIN_xxx_xxx_lcd (maybe HV vs DEN mode, or RGB vs YCbCr) FD50h - IO_whatever_FD50h (no visible effect...?) |
Tianma 24bit RGB+HV : FC00h=05h, FD34h..FD43h=11h, FD50h=0Bh Innolux 24bit RGB+DEN : FC00h=00h, FD34h..FD43h=22h, FD50h=0Fh |
_______________________________ PLL Registers _______________________________ |
0? hangs CPU? 1-2? OSDcharerror+hang? 3 unknown, no visible effect 4 OSD_BG_ONLY (no TEXT) 5 scanlinefreeze(AV+OSD) 6-7 unknown, no visible effect |
0-1 unknown, no visible effect 2 AV filled by most-recent AV pixel color (OSD+backdrop still work) 3 kills TFT screen output (dotclk switched HIGH permanently) 4 DANGER: hangs ADC 5 stops PWM (randomly gets stuck at MAX or MIN backlight level) 6-7 unknown, no visible effect |
bit0 NoSignal, withSmallVsyncRoll bit6 Darker(AV+OSD) -- PWM is (almost) twice as fast as usually bit7 NoSignal, occassionally/shortly AV scanlines shown twice/at half width |
bit0 force NTSC color, or somewhat other/wrong color clock? bit1,3-7 force NoSignal bit2 force gray AV at wrong Xloc bit0,1 C64: temporarily enables C64 image |
bit4: flipped changes dotclk to 16.12MHz (instead 8.06) ;\shift/divider bit5: flipped changes dotclk to 32.26MHz (instead 8.06) ;/for dotclk? bit6-7: no signal (no AV image) bit7: no effect on dotclk... but much more white snow |
bit2: freeze dotclk (get stuck in LOW or HIGH state) bit3: freeze snow (backdrop get stuck with all WHITE or BLUE/BLACK pixels) |
FD0Ah dotclk: MULTIPLY by N 2Bh = (default) 8.06MHz (0.187MHz * 43) 2Ah = (bit0 flipped) 7.88 29h = (bit1 flipped) 7.68 2Fh = (bit2 flipped) 8.82 23h = (bit3 flipped) 6.56 (0.187MHz * 35) 3Bh = (bit4 flipped) 11.06 (0.187MHz * 59) 0Bh = (bit5 flipped) 2.06 (0.187MHz * 11) 6Bh = (bit6 flipped) 15.74 MAX (0.187MHz * 84) ABh = (bit7 flipped) 15.74 MAX (0.187MHz * 84) |
FD0Fh dotclk: DIVIDE by N (with some odd effects in some cases) 03h = (default) 8.06MHz (15.72MHz / 1.95) (24.20MHz / 3) 02h = (bit0 flipped) 12.10MHz (15.72MHz / 1.3) (24.20MHz / 2) 01h = (bit1 flipped) 15.72MHz (15.72MHz / 1) (24.20MHz / 1.54) ;odd 07h = (bit2 flipped) 3.46MHz (15.72MHz / 4.54) (24.20MHz / 7) 0Bh = (bit3 flipped) 2.20MHz (15.72MHz / 7.14) (24.20MHz / 11) 13h = (bit4 flipped) 1.27MHz (15.72MHz / 12.37) 23h = (bit5 flipped) 0.69MHz (15.72MHz / 22.78) (24.20MHz / 35) 43h = (bit6 flipped) unstable (0.3-0.4MHz) (stutters) ;<-- odd 83h = (bit7 flipped) 15.74MHz MAX (MAX) ;<-- odd |
FD14h dotclk: DIVIDE by N 03h = (default) 8.06MHz (24.20 / 3) 02h = (bit0 flipped) 12.10MHz (24.20 / 2) 01h = (bit1 flipped) 24.20MHz (24.20 / 1) ;<-- unlike FD0Fh 07h = (bit2 flipped) 3.46MHz (24.20 / 7) 0Bh = (bit3 flipped) 2.20MHz 13h = (bit4 flipped) 1.27MHz (24.20 / 19) 23h = (bit5 flipped) 0.69MHz 43h = (bit6 flipped) 0.36MHz ;<-- unlike FD0Fh 83h = (bit7 flipped) 24.20MHz ;<-- unlike FD0Fh |
FD15h dotclk: DIVIDE by N 02h = (default) 8.06MHz (16.12 / 2) 03h = (bit0 flipped) 5.38MHz (16.12 / 3) 00h = (bit1 flipped) 16.12MHz 06h = (bit2 flipped) 2.68MHz (16.12 / 6) 0Ah = (bit3 flipped) 1.61MHz (16.12 / 10) 12h = (bit4 flipped) 0.89MHz 22h = (bit5 flipped) 0.47MHz 42h = (bit6 flipped) 0.24MHz 82h = (bit7 flipped) 16.12MHz |
______________________________ Unused Registers ______________________________ |
| AMT630A - FExxh - AV Registers (Composite Video Input) |
____________________________ AV Status Registers ____________________________ |
video DETECT... OFTEN used (bit1,bit2 tested) |
...status (boldness, bit0 tested, used by only ONE opcode) |
...status (sharpness, bit2-5) |
bit2 = PAL/NTSC and/or 50/60 Hz |
...status (bit6 and bit0-3 used) bit0,1,2,3=ErrorFlag(s)) bit4:Have Signal on currently selected pin ;\CVBS1 and CVBS3 inputs bit6:Have Signal on currently de-selected pin ;/ |
16bit status/counter? (NoSignal:0FFFh, C64:0287h..028Bh=647..651) |
_________________________ AV Misc Control Registers _________________________ |
bit0 ForcePALcolors_ButYetPAL60getsWrongYloc, bit2 ForcePALcolors_But_Only_If_FE00h.bit7 is toggled (similar as FE01h.bit0, but HERE bit2 has NO effect if FE00h.bit7=x) |
initially 00h, bit6 is manipulated later on |
bit0 sometimes causes NoSignal, and simetimes FreezesCurrentScanline
(THAT affecting BOTH OSD AND AV !!!)
bit1 move AV image 1pix UP, and ca.8pix RIGHT
bit2-7 NOT R/W
|
bit0: NICE: LessPalArtifactsOnSNES bit1: Similar as bit0, plus magenta-line at bottom of red-snes-screen |
______________________ AV Sensitivity Control Registers ______________________ |
set to 00h=max, 05h=med, 09h=low, also checked if 05h bit2,3:PixelBoldness |
initially B1h, modified/used later |
____________________ AV Input Select and On/Off Registers ____________________ |
Clear IO_AV_video_on_off bit3,4 Change IO_AV_input_select_reg_0 bit6,7 Set IO_AV_video_on_off bit3,4 Change IO_AV_input_select_reg_1 bit4,5 |
- - - IO_AV_video_on_off - - - | IO_AV_input_select_reg_0 - - - | | IO_AV_input_select_reg_1 Input FED7h.bit3-4 FED8h.bit6-7 FEDCh.bit4-5 OLDER FIRMWARE: AV1 0-then-3 2 0 ;<-- CVBS1 AV2 0-then-3 2 3 ;<-- stripes when CVBS3 has signal AV3 0-then-3 0 2 ;<-- CVBS3 Invalid 0-then-3 3 3 ;<-- stripes when CVBS3 has signal NEWER FIRMWARE: AV1 0-then-3 0 ! 2 ! ;<-- AV2 0-then-3 0 ! 3 ;<-- AV3 0-then-3 2 ! 0 ! ;<-- Invalid 0-then-3 3 3 ;<-- |
bit0+1+6+7:disable SNOW (freeze backdrop-color or snow-color,
and occassionally also freeze current OSD scanline!)
|
C64: bit7=whitish stripes when C64 ON
;SNES: bit7=ShortlyWhiteStripes...ThenAllWhite (looks as if snow/random
generator ends up with all-white pixels)
|
bit4: Toggle=BlueBackdrop(without snow),
Untoggle: ShortlyNoSignal(with snow)ThenNormalPicture
bit5: NoSignal, or, if C64 powered on AV2: white picture with
blue/rolling hsync/vsync signals?
bit6: BlueBackdrop(without snow, except a VERY FEW random/snow pixels
in some rolling-screen-half)
bit6: Like bit6, but with a little bit more random/now pixels)
bit7: C64: minimal SNOW when C64 ON
|
____________________________ AV Config Registers ____________________________ |
bit1 Less Boldness bit6 Dithered All Green Image (GREEN !!!) |
________________________ AV Internal Status Registers ________________________ |
_______________________ AV Internal Control Registers _______________________ |
bit0-2 Slight horiz.position changes
bit3 BlurRightScreenEdge
bit4 NoSignal
bit5 C64 does PERFECTLY SHOW C64 IMAGE! (still shows SNOW if C64=Off)
bit6 Wrong Color (Lightblue instead Red in SnesDiag, Washy if C64 on
AV2... hmmm or is that S-Video with Chroma from AV2?)
bit7 no visible effect
|
FE1Dh.bit7: NOT RW FE1Eh.bit7: NOT RW FE1Fh.bit7: NOT RW FE39h.bit4-7: NOT RW FE3Fh.bit1-7: NOT RW FE4Bh.bit7: NOT RW FE4Dh.bit3-7: NOT RW FE4Fh.bit7: NOT RW FE8Bh.bit7: NOT RW FE8Dh.bit3-7: NOT RW FE8Eh.bit5-7: NOT RW FEA2h.bit3-7: NOT RW FEB2h.bit7: NOT RW FEB6h.bit5-7: NOT RW FEB7h.bit1-7: NOT RW FED1h.bit7: NOT RW FED3h.bit2-7: NOT RW |
FE00h.bit4 Vertical.boldness
FE00h.bit5 Temporarily NoSignal
FE00h.bit7 Force_NTSC_Colors?
FE0Dh:bit7 Untoggle=BlinksAvWhiteRecalib?
FE0Fh.bit0-2 Change=TemporarilyNoSignal
FE0Fh.bit3 ForcePALcolors_ButYetPAL60getsWrongYloc
(similar as FE01h.bit0, but HERE effect is inverse if
FE00h.bit7=x --> then forces NTSC colors)
FE11h.bit2 ShortColorRollThenShowDitheredBlackWhiteAvImage
FE11h.bit4-7 ShortColorRollThenShowDitheredBlackWhiteAvImage
FE17h.bit1 Boldness
FE17h.bit4-5 BoldnessWithContrast
FE17h.bit6-7 PermanentlyToggleColoredAndDitheredBlackWhiteLines
FE18h.bit1-2 BoldnessAndRightScreenEdge
FE18h.bit6-7 PermanentlyToggleColoredAndDitheredBlackWhiteLines
FE1Dh.bit6 NoSignalOrWeirdColorRoll
FE1Eh.bit6 NoSignalOrWeirdColorRoll
FE2Dh.bit7 ShortColorRollThenBlackWhiteDither
FE31h.bit7 NoSignal
FE3Ch.bit5 Boldness
FE3Ch.bit6 BoldnessAndWashyBackground(SnesLooksAsWashyAsC64)
FE3Ch.bit7 BoldnessBrighterBlack
FE3Dh.bit6 UltraWashyBlurr
FE3Dh.bit7 RollingImageAndBlackWhiteDither
FE41h.bit6 TrueSnow?(not the artifical snow effect)
FE41h.bit7 freezeSNOW (stuck BG or WHITE) and/or snow with wandering bars
FE41h.bit6-7 C64:vague picture/sync traces? (uh, was this FE41h, not Fx41h?)
FE43h Somewhat Lumafactor/Lumaoffset for white-pixels getting
brighter, or, if bit7 changed: white pixels are becoming BLACK
FE44h.bit5 LessBoldness
FE44h.bit6 AllMuchBrighter(including brighter black)
FE44h.bit7 AllVERYMuchBrighter(including brighter black)
FE45h.bit7 MonochromeImage(not dithered), with Washyness if C64 on AV2
FE47h.bit7 ReddishMagentaInsteadRed, with Washyness if C64 on AV2
FE48h.bit6 BlackWhiteDitheredImage
FE4Eh.bit6 C64: Untoggling FE4Eh.6 shows C64 image for short moment
(no effect on SNES image)
FE50h.bit6-7 C64: does show C64 image going on/off (no effect on SNES)
FE55h.bit4 AlmostCompletelyOmitsSomePalScanlines(instead of resampling
them from PAL to 240pix-LCD-resolution)
FE55h.bit5 SameAsBit4(but affecting OTHER lines)
FE60h.bit1 When changed: ShortlyFlashesOrShortlyNoSignal
FE60h.bit3 SNES: dims white to BluishGray and/or shortly NoSignal
FE60h.bit3 C64: rolling white stripes when C64 ON
FE80h.bit7 ForcesBlackImage
FEB4h.bit7 Maybe S-Video (picks Snes/Luma from AV1, but C64/Chroma from
AV2, showing hatchy blue borders at wrong hsync)
FEB7h.bit0 Moves image 1pix LEFT
FEC8h.bit0 DitheredBlackWhite
FEC8h.bit7 Move image ca.80pix RIGHT and ca.12pix UP
FECAh.bit0 UntogglingShortlyDimsBrightness
FECAh.bit1 UntogglingShortlyBlinksWhitePixels
FED1h.bit5-6 UponChanges: ShortlyNoSignal
FED4h.bit1 OverBright (andWashyIfC64 is powered on AV2)
FED6h.bit3 Snowy random Red/Magenta pixels (instead of SNES with Red
background) (and if C64 powered on AV2: diagonally striped
Red/Magenta) (might be also S-Video, chroma from AV2?)
FED6h.bit7 ShortlyNoSignal, then UberOverBrightImage (Washy if C64 on AV2)
FED6h.bit7 C64: does show C64 image, only once and then, goes on and off
;C64: FF20h.6-7: C64/SNOW color ;XXX why FFxxh? THIS is FExxh!!!
: (also, FE20h would be read-only)
;C64: FF4Ah.7/FF4Bh.7/C64: bluish ;XXX why FF4xh? THIS is FE4xh!!!
|
____________________________ AV Unused Registers ____________________________ |
| AMT630A - FFxxh - LCD Registers (gamma/brightness/etc and IR) |
03h,06h,0Ah,0Eh,14h,1Ah,21h,29h,34h,40h,4Dh,59h,66h,73h,81h,8Eh, 9Ch,A7h,B1h,BAh,C2h,CAh,D0h,D7h,DDh,E2h,E7h,ECh,F1h,F6h,FAh |
03h,07h,0Bh,10h,15h,1Bh,22h,2Ah,34h,3Fh,4Bh,58h,65h,72h,7Eh,89h 96h,A2h,AEh,BAh,C4h,CDh,D5h,DCh,E2h,E7h,ECh,F0h,F4h,F8h,FBh |
07h,10h,1Ah,23h,2Dh,35h,3Ch,43h,4Ah,51h,56h,5Ch,62h,68h,6Eh,74h 7Ah,81h,88h,8Fh,96h,9Dh,A4h,ABh,B2h,BAh,C1h,C9h,D2h,DDh,ECh |
0-3 Snow Amount (00h,01h=50% White, 06h=ManyWhite, 08h=FewWhite, etc.) 4-6 Snow Width (00h-07h = 1-8 pixels) 7 ??? |
0 ??? affects AV picture NTSC? bright? 1-4 ??? 5 ??? should be 1 (weirdly firmware often rewrites it as so) 6 ??? 7 Snow Enable (0=Off, 1=On) |
bit0 AV bolder/brighter/smeared pixels bit1-2 also bolder? bit3 VeryBlurry bit4,6 C64 becomes bluish? |
0 Darker OSD colors? 1-7 ??? |
0-6 ??? 7 ??? (firmware sets/clears this bit) |
for AV: 0 Swap Red/Blue 1 Mess 2 Dim? 3 AV_OFF/BLACK (show OSD only) 7 C64: bluish on C64 |
FF00h.bit0/1: Affect AV color/brightness or so, maybe GammaRampMode/Enable? FFCCh.bit6: Forces whole screen Mintgreen? (disables AV and OSD) FFCCh.bit7: Brighter black |
Power-Up/Reset: 65h,C0h,DAh,0Dh,3Dh,19h,DAh,CDh,1Ah,3Dh,19h,81h Older firmware: 1Ah,06h,D4h,D2h,F1h,0Eh,15h,E4h,F6h,F1h,1Bh,81h Newer firmware: 11h,00h,00h,E9h,E1h,0Eh,09h,EEh,F4h,F1h,23h,81h |
FFB8h.bit7 ;-changing this bit causes BrighterBlack FFD1h.bit6 ;-changing this bit causes BrighterBlack |
________________________ Infrared IR REMOTE Registers ________________________ |
____________________________ LCD Unused Registers ____________________________ |
| AMT630A - Component Lists & Pinouts |
mainboard: "ZCD630A-3.5D_V1.1" main chip: 64pin AMT630A (video controller with 8031 cpu) firmware: 8pin "MK, 25D40BTIG, 1720" (512kbyte spi flash, D=DualDataPin) voltage regulator 1: 8pin "XL1509" (pin1=Vin/12V, pin2=Vout/5V) voltage regulator 2: 3pin (5V to 3.3V) backlight driver: 6pin "7001" (Micrel MIC3287 or compatible) connectors: 54pin display, 2pin keypad, 4pin video/supply, 4pin sio/unused display: "RoHS 1580005880 111020, TM035KDH03, 76DK14A04A1 OMP 11111009, 1" |
mainboard: "BO-39-Y-7795BH1" ? main chip: 64pin "AMT630A, G171800030" firmware spi flash: "MK, xxD040BTIG, S782A1" voltage regulator: "RZC2013S, SZ82" backlight driver "D2AxD ?" connectors: 40pin display, 2pin keypad, 4pin video/supply, 4pin sio/unused display "GP Innolux Display, AT050TN33 V.1 AA0500004101, S/N: 895W 001-000WB" crystal "X27.000" |
3.5 inch 4:3 320x240 4.3 inch 16:9 480x272 5.0 inch 16:9 480x272 or 800x480 5.6 inch 4:3 1024x768 or 320x234? or 800x600? 7.0 inch 16:9 1024x600 or 480x234? 8.0 inch 4:3 1024x768 |
AV-to-USB video grabbers |
Pin TYPE Function 1 A CVBS1 ;-external video YELLOW 2 A CVBS2 ;-GNDed 3 A CVBS3 ;-external video WHITE 4 A VCOM_ADC ;- 5 P AVSS_ADC (GND) 6 D P03 REMOTE ;- 7 A P00 SAR2 8 A P01 SAR1 9 A P02 SAR0 ;-Keypad 10 P DVDD 3.3V 11 P GND 12 P VDD 1.2v (build-in LDO for 1.2v core power) 13 P AGND (AVSS33_ANA) 14 A XTAL_OUT ;\27MHz 15 A XTAL_IN ;/ 16 P AVDD 3.3V --- 17 D P10 SPI_CS ;\ 18 D P11 SPI_SI ; SPI FLASH 19 D P12 SPI_SO ; 20 D P13 SPI_CLK ;/ 21 P DVDD 3.3V 22 P VDD 1.2v (build-in LDO for 1.2v core power) 23 P GND 24 D P14 cpu_rstn R0 VOS tcon_r0 ituVDE sVSY ;\LCD. D 25 D P15 cpu_cs R1 HOS tcon_r1 ituHDE sHSY ; LCD. D 26 D P16 cpu_rs R2 DOE tcon_r2 ituDEO sDEN ; LCD. D 27 D P17 cpu_wr R3 DCK tcon_r3 ituclko sCLK ; LCD. D 28 D P20 cpu_rd R4 B7 tcon_r4 itu_d7 sD7 ; LCD. D 29 D P21 cpu_d17 R5 B6 tcon_r5 itu_d6 sD6 ; LCD. D 30 D P22 cpu_d16 R6 B5 STVR itu_d5 sD5 ; LCD. D 31 D GPIO0 cpu_d15 R7 B4 STVL itu_d4 sD4 ;/LCD. D (blue.7) 32 D GPIO1 cpu_d14 G0 B3 tcon_g0 itu_d3 sD3 ;\LCD. D --- 33 D GPIO2 cpu_d13 G1 B2 tcon_g1 itu_d2 sD2 ; LCD. D 34 D GPIO3 cpu_d12 G2 B1 tcon_g2 itu_d1 sD1 ; LCD. D 35 D GPIO4 cpu_d11 G3 B0 tcon_g3 itu_d0 sD0 ; LCD. D 36 D P23 cpu_d10 G4 G7 tcon_g4 ; LCD. D 37 D P24 cpu_d9 G5 G6 tcon_g5 ; LCD. D 38 D P25 cpu_d8 G6 G5 CKV ; LCD. D 39 D P26 cpu_d7 G7 G4 OEV ;/LCD. D (green.7) 40 P DVDD 3.3V 41 P VDD 1.2v (build-in LDO for 1.2v core power) 42 P GND 43 D GPIO5 cpu_d6 B0 G3 tcon_b0 itu_d0' sD0' ;\LCD. D 44 D GPIO6 cpu_d5 B1 G2 tcon_b1 itu_d1' sD1' ; LCD. D 45 D GPIO7 cpu_d4 B2 G1 tcon_b2 itu_d2' sD2' ; LCD. D 46 D GPIO8 cpu_d3 B3 G0 tcon_b3 itu_d3' sD3' ; LCD. D 47 D GPIO9 cpu_d2 B4 R7 tcon_b4 itu_d4' sD4' ; LCD. D 48 D GPIO10 cpu_d1 B5 R6 tcon_b5 itu_d5' sD5' ; LCD. D --- 49 D P27 cpu_d0 B6 R5 STHR itu_d6' sD6' ; LCD. D 50 D P30 cpu_rd B7 R4 POL itu_d7' sD7' ;/LCD.35 D23 (red.7) 51 D P31 cpu_wr DCK R3 tcon_clk ituclko' sCLK' ;\LCD.38 CLK 52 D P32 cpu_rs DOE R2 STHL ituDEO' sDEN' ; LCD.52 DEN 53 D P33 cpu_cs HOS R1 OEH ituHDE' sHSY' ; LCD.36 HSYNC 54 D P34 cpu_rstn VOS R0 tck2 ituVDE' sVSY' ;/LCD.37 VSYNC 55 D P35 DC_PWM0 ;backlight driver (via 1K ohm) 56 D P36 DC_PWM1 TXD'' ;display spi.dta (via 33 ohm) 57 D P37 DC_PWM2 RXD'' ;display spi.clk (via 33 ohm) 58 D P07 DC_PWM3 RXD' ;display spi.cs (via 33 ohm) 59 D P06 DC_PWM2' TXD' ;display spi.reset (via 33 ohm) 60 D P04 SDA TXD ;to external connector 61 D P05 SCL RXD ;to external connector 62 P DVDD 3.3V 63 D RESET ;-reset (active HIGH) 64 P AVDD_ADC 3.3V |
1 /CS 2 DO 3 /WP (VCC'ed) 4 GND 5 DI 6 CLK 7 /HOLD (VCC'ed) 8 VCC (3.27V) (even when video off) |
1 SW Switch Node ("Input"): Internal power bipolar collector
2 GND Ground
3 FB Feedback (input): Output voltage sense node.
4 EN Enable (input): High=enable, Low=Shuts Down ;PWM
5 OVP Overvoltage Protection (Input): Connect to the output ;LED Anode
6 VIN Supply (input): 2.8V to 6.5V for internal circuitry ;5V
|
Pin Symbol I/O Function Remark 1 VLED- P Power for LED backlight cathode ;\backlight 2 VLED+ P Power for LED backlight anode ;/ 3 GND P Power ground ;\supply 4 VDD P Power voltage ;/ 5 R0 I Red data (LSB) 6 R1 I Red data 7 R2 I Red data 8 R3 I Red data 9 R4 I Red data 10 R5 I Red data 11 R6 I Red data 12 R7 I Red data (MSB) 13 G0 I Green data (LSB) 14 G1 I Green data 15 G2 I Green data 16 G3 I Green data 17 G4 I Green data 18 G5 I Green data 19 G6 I Green data 20 G7 I Green data (MSB) 21 B0 I Blue data (LSB) 22 B1 I Blue data 23 B2 I Blue data 24 B3 I Blue data 25 B4 I Blue data 26 B5 I Blue data 27 B6 I Blue data 28 B7 I Blue data (MSB) 29 GND P Power ground 30 CLK I Pixel clock 31 DISP I Display on/off 32 NC - No Connection 33 NC - No Connection 34 DE I Data Enable 35 NC - No Connection 36 GND P Power ground 37 X1 I/O Right electrode - differential analog ;\ 38 Y1 I/O Bottom electrode - differential analog ; touchpad 39 X2 I/O Left electrode - differential analog ; (unused) 40 Y2 I/O Top electrode - differential analog ;/ I: input, O: output, P: Power |
1 LED_Cathode ;\ ;\GND via 2.2 ohm 2 LED_Cathode ; backlight ;/ 3 LED_Anode ; ;\ 4 LED_Anode ;/ ;/ 5 NC ;\ 6 NC ; not connect 7 NC ;/ 8 RESET ;-reset 9 SPENA ;\ 10 SPCK ; SPI bus 11 SPDA ;/ 12 D00 ;\ 13 D01 ; 14 D02 ; 15 D03 ; LCD 16 D04 ; 17 D05 ; 18 D06 ; 19 D07 ;/ 20 D08 ;\ 21 D09 ; 22 D10 ; 23 D11 ; LCD 24 D12 ; 25 D13 ; 26 D14 ; 27 D15 ;/ 28 D16 ;\ 29 D17 ; 30 D18 ; 31 D19 ; LCD Red (in default 24bit+HV mode) 32 D20 ; 33 D21 ; 34 D22 ; 35 D23 ;/ 36 HSYNC ;\LCD Sync (in default 24bit+HV mode) 37 VSYNC ;/ 38 CLK ;-data clock 39 NC ;\not connect 40 NC ;/ 41 VDD ;\power 3.3V 42 VDD ;/ 43 NC ;\ 44 NC ; 45 NC ; not connect 46 NC ; 47 NC ; 48 NC ; 49 NC ; 50 NC ; 51 NC ;/ 52 DEN ;-LCD data enable 53 GND ;\ground 54 GND ;/ |
AMT630A side PC Side (36pin Centronics or 25pin SUBD) DTA.W FLASH.pin5 ----[1K]---- D0 CNTR.pin2 SUBD.pin2 CLK FLASH.pin6 ----[1K]---- D1 CNTR.pin3 SUBD.pin3 /CS FLASH.pin1 ----[1K]---- D2 CNTR.pin4 SUBD.pin4 DTA.R FLASH.pin2 --[74HCxx]-- BUSY CNTR.pin11 SUBD.pin11 RESET AMT630A.pin63 ----|<|----- /INIT CNTR.pin31 SUBD.pin16 GND SUPPLY.Black ------------ GND CNTR.pin19-30 SUBD.pin18-25 |
| Index |